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integrated silicon solution, inc. www.issi.com 1 rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll 64k x 16 low voltage, ultra low power cmos static ram features ? high-speed access time: 35ns, 45ns, 55ns ? cmos low power operation: 15 mw (typical) operating 1.5 w (typical) cmos standby ? ttl compatible interface levels ? single power supply 1.65v--2.2v v d d (62wv6416d all) 2.3v--3.6v v d d (65wv6416dbll) ? fully static operation: no clock or refresh required ? three state outputs ? data control for upper and lower bytes ? industrial and automotive temperature support ? 2cs option available ? lead-free available description the issi is62/65wv6416dall and is62/65wv6416dbll are high-speed, 1m bit static rams organized as 64k words by 16 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected) or when cs1 is low , cs2 is high and both lb and ub are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. a data byte allows upper byte (ub) and lower byte (lb) access. the is62/65wv6416dall and is62/65wv6416dbll are packaged in the jedec standard 48-pin mini bga (6mm x 8mm) and 44-pin tsop (type ii). functional block diagram october 2009 a0-a15 cs1 oe we 64k x 16 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb cs2
2 integrated silicon solution, inc. www.issi.com rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll pin configurations 48-pin mini bga (6mm x 8mm) (package code b) pin descriptions a0-a15 address inputs i/o0-i/o15 data inputs/outputs cs1, cs2 chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v d d power gnd ground 48-pin mini bga (6mm x 8mm) 2 cs option (package code b2) 44-pin mini tsop (type ii) (package code t) 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 cs2 i/o 8 ub a3 a4 cs1 i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 nc a7 i/o 3 v dd v dd i/o 12 nc nc i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 nc i/o 8 ub a3 a4 csi i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 nc a7 i/o 3 v dd v dd i/o 12 nc nc i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1 i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a15 a14 a13 a12 nc a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 nc
integrated silicon solution, inc. www.issi.com 3 rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll absolute maximum ratings (1) symbol parameter value unit v t e r m terminal voltage with respect to gnd C0.5 to v d d + 0.5 v v d d v d d relates to gnd C0.3 to 4.0 v t s t g storage temperature C65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) symbol parameter conditions max. unit c i n input capacitance v i n = 0v 6 pf c i/o input/output capacitance v o u t = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v d d = 3.3v. truth table i/o pin mode we cs1 cs2 oe lb ub i/o0-i/o7 i/o8-i/o15 v d d current not selected x h x x x x high-z high-z i s b 1 , i s b 2 x x l x x x high-z high-z i s b 1 , i s b 2 x x x x h h high-z high-z i s b 1 , i s b 2 output disabled h l h h l x high-z high-z i c c h l h h x l high-z high-z i c c read h l h l l h d o u t high-z i c c h l h l h l high-z d o u t h l h l l l d o u t d o u t write l l h x l h d i n high-z i c c l l h x h l high-z d i n l l h x l l d i n d i n
4 integrated silicon solution, inc. www.issi.com rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll ac test loads figure 1. r1 5 pf including jig and scope r2 output vtm figure 2. ac test conditions parameter unit unit unit (2.3v-3.6v) (3.3v + 5%) (1.65v-2.2v) input pulse level 0.4v to v d d - 0.3v 0.4v to v d d - 0.3v 0.4v to v d d - 0.3v input rise and fall times 1v/ ns 1v/ ns 1v/ ns input and output timing vdd /2 vdd + 0.05 0.9v and reference level (v ref ) 2 output load see figures 1 and 2 see figures 1 and 2 see figures 1 and 2 r1 ( ? ) 317 317 13500 r2 ( ? ) 351 351 10800 v t m (v) 3.3v 3.3v 1.8v r1 30 pf including jig and scope r2 output vtm
integrated silicon solution, inc. www.issi.com 5 rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll dc electrical characteristics (over operating range) v d d = 2.3v-3.6v symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C1.0 ma 1.8 v v o l output low voltage v d d = min., i o l = 2.1 ma 0.4 v v i h input high voltage 2.0 v d d + 0.3 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v d d = 3.3v + 5% symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C1 ma 2.4 v v o l output low voltage v d d = min., i o l = 2.1 ma 0.4 v v i h input high voltage 2 v d d + 0.3 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v d d = 1.65v-2.2v symbol parameter test conditions v d d min. max. unit v o h output high voltage i o h = -0.1 ma 1.65-2.2v 1.4 v v o l output low voltage i o l = 0.1 ma 1.65-2.2v 0.2 v v i h input high voltage 1.65-2.2v 1.4 v d d + 0.2 v v i l (1) input low voltage 1.65-2.2v C0.2 0.4 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v ac (pulse width < 10 ns). not 100% tested.
6 integrated silicon solution, inc. www.issi.com rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll power supply characteristics (1) (over operating range) -35 -45 -55 symbol parameter test conditions min. max. min. max. min. max. unit i c c v d d dynamic operating v d d = max., com. 8 6 5 ma supply current i o u t = 0 ma, f = f m a x ind. 12 8 7 ce = v i l auto. 15 12 12 v i n v d d C 0.3v, or typ. (2) 5 v i n 0.4v i c c 1 operating v d d = max., com. 2.5 2.5 2.5 ma supply current i o u t = 0 ma, f = 0 ind. 2.5 2.5 2.5 ce = v i l auto. 5 5 5 v i n v d d C 0.3v, or v i n 0.4v i s b 2 cmos standby v d d = max., com. 2 2 2 a current (cmos inputs) cs1 v d d C 0.2v, ind. 4 4 4 cs2 0.2v, auto 18 18 18 v i n v d d C 0.2v, or typ. (2) 0.6 v i n 0.2v, f = 0 or ulb control v d d = max., cs1 = v i l , cs2=v i h v i n 0.2v, f = 0; ub / lb = v d d C 0.2v note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. operating range ( v d d ) ran ge ambient temperatur e v d d (45 n s ) v d d (35 n s ) commercial 0c to +70c 2.3v-3.6v 3.3v +5% industrial C40c to +85c 2.3v-3.6v 3.3v+5% operating range ( v d d ) r ange ambient temperature v d d s peed commercial 0c to +70c 1.65v-2.2v 45ns industrial C40c to +85c 1.65v-2.2v 55ns automotive C40c to +125c 1.65v-2.2v 55ns operating range ( v d d ) rang e ambient temperature v d d (45 n s ) automotive C40c to +125c 2.3v-3.6v
integrated silicon solution, inc. www.issi.com 7 rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll read cycle switching characteristics (1) (over operating range) 35 ns 45 ns 55 ns symbol parameter min. max. min. max. min. max. unit t r c read cycle time 35 45 55 ns t a a address access time 35 45 55 ns t o h a output hold time 10 10 10 ns t a c s 1/ t a c s 2 cs1/cs2 access time 35 45 55 ns t d o e oe access time 10 20 25 ns t h z o e (2) oe to high-z output 0 10 0 15 0 20 ns t l z o e (2) oe to low-z output 3 5 5 ns t h z c s 1/ t h z c s 2 (2) cs1/cs2 to high-z output 0 10 0 15 0 20 ns t l z c s 1/ t l z c s 2 (2) cs1/cs2 to low-z output 5 5 10 ns t b a lb, ub access time 35 45 55 ns t h z b lb, ub to high-z output 0 15 0 15 0 20 ns t l z b lb, ub to low-z output 0 0 0 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v d d -0.2v/v d d -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
8 integrated silicon solution, inc. www.issi.com rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll data valid previous data valid t aa t oha t oha t rc d out address ac waveforms read cycle no. 1 (1,2) (address controlled) (cs1 = oe = v i l , cs2 = we = v i h , ub or lb = v i l ) t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzcs1/ t hzcs2 address oe cs1 cs2 dout lb , ub t hzb t ba t lzb ac waveforms read cycle no. 2 (1,3) ( ,cs2,, and / controlled) notes: 1. e is high for a read cycle. 2. the device is continuously selected. , , , or = v i l . c s2=we=v i h . 3. address is valid prior to or coincident with low transition.
integrated silicon solution, inc. www.issi.com 9 rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll write cycle switching characteristics (1,2) (over operating range) 35 ns 45 ns 55 ns symbol parameter min. max. min. max. min. max. unit t w c write cycle time 45 45 55 ns t s c s 1/ t s c s 2 cs1/cs2 to write end 35 35 45 ns t a w address setup time to write end 35 35 45 ns t h a address hold from write end 0 0 0 ns t s a address setup time 0 0 0 ns t p w b lb, ub valid to end of write 35 35 45 ns t p w e we pulse width 35 35 40 ns t s d data setup to write end 20 20 25 ns t h d data hold from write end 0 0 0 ns t h z w e (3) we low to high-z output 20 20 20 ns t l z w e (3) we high to low-z output 5 5 5 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4v to v d d -0.2v/v d d -0.3v and output loading specifed in figure 1. 2. the internal write time is defned by the overlap of cs1 low, cs2 high and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. notes: 1. write is an internally generated signal asserted during an overlap of the low states on the cs1 , cs2 and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = (cs1) [ (lb) = (ub) ] (we). ac waveforms write cycle no. 1 (1,2) (cs1 controlled, oe = high or low) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din lb, ub t pwb
10 integrated silicon solution, inc. www.issi.com rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll write cycle no. 2 (we controlled: oe is high during write cycle) write cycle no. 3 (we controlled: oe is low during write cycle) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din
integrated silicon solution, inc. www.issi.com 11 rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll write cycle no. 4 (ub/lb controlled) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 t hd t sa t hzwe address cs1 ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha high cs2
12 integrated silicon solution, inc. www.issi.com rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll data retention switching characteristics symbol parameter test condition min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 1.2 3.6 v i d r data retention current v d d = 1.2v, cs1 v d d C 0.2v com. 0.4 2 a ind. 4 auto. 18 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note: 1. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. data retention waveform ( cs1 controlled) data retention waveform (cs2 controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd data retention mode v dd cs2 0.2v t sdr t rdr v dr cs2 gnd data retention mode
integrated silicon solution, inc. www.issi.com 13 rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll ordering information is62wv6416dall (1.65v - 2.2v) industrial range: -40c to +85c speed (ns) order part no. package 55 is62wv6416dall-55bli mini bga (6mm x 8mm), lead-free is62wv6416dall-55tli tsop type ii, lead-free is62wv6416dbll (2.3v -3.6v) industrial range: -40c to +85c speed (ns) order part no. package 45 (35) 1 is62wv6416dbll-45ti tsop type ii is62wv6416dbll-45tli tsop type ii, lead-free is62wv6416dbll-45bi mini bga (6mm x 8mm) is62wv6416dbll-45bli mini bga (6mm x 8mm), lead-free is62wv6416dbll-45b2li mini bga (6mm x 8mm), 2cs, lead-free note: 1. speed = 35ns for v d d = 3.3v5%. speed = 45ns for v d d = 2.3v-3.6v is65wv6416dbll (2.3v -3.6v) automotive range: -40c to +125c speed (ns) order part no. package 45 is65wv6416dbll-45tla3 tsop type ii, lead-free is65wv6416dbll-45bla3 mini bga (6mm x 8mm), lead-free
14 integrated silicon solution, inc. www.issi.com rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/12/2008 package outline
integrated silicon solution, inc. www.issi.com 15 rev. a 09/29/09 is62wv6416dall/dbll is65wv6416dall/dbll 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline

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